The present invention relates broadly to an input buffer apparatus, and in particular to a Schmitt-triggered TTL to CML input buffer apparatus.
The state of the art of input buffer apparatus is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Pat. Nos.:
U.S. Pat. No. 4,607,177 issued to Lechner on Aug. 19, 1986; PA1 U.S. Pat. No. 4,719,369 issued to Denda on Jan. 12, 1988; PA1 U.S. Pat. No. 4,737,663 issued to Varadarajan on Apr. 12, 1988; PA1 U.S. Pat. No. 4,783,607 issued to Hsieh on Nov. 8, 1988; and
U.S. Pat. No. 4,806,800 issued to Khan on Feb. 21, 1989.
The Lechner patent describes a circuit arrangement for level conversion of TTL-logic levels to ECL-logic levels with at least one emitter-coupled current switch having an input addressable by TTL-logic levels and an output from which ECL-logic levels can be taken off, including a first current switch formed of two emitter-coupled npn-transistors and a second current switch formed of two emitter-coupled pnp-transistors.
The Denda patent is directed to a B-MOS implementation of a Schmitt trigger circuit with an improved switching speed.
The Varadarajan patent discloses a current source arrangement for three-level emitter-coupled logic and four-level current mode logic which utilizes a low drop current source that is incorporated in the series-gated arrangement.
The Hsieh patent discusses a TTL/CMOS compatible input buffer circuit which utilizes a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger.
The Khan patent describes a high speed low power electrical circuit for converting true TTL level signals to true ECL level signals. The circuit only has a single buffer delay with some small additional delay due to an input emitter follower stage.
While the above-cited prior art patents are instructive, it is clear that a need remains to provide a TTL to CML input buffer apparatus which solves the shortcomings of the prior art. The present invention is intended to satisfy that need.